Last Update: 03 Jun 2018
December 2009 – November 2012

COMPLEX – COdesign and power Management in PLatform-based design space EXploration is an EU funded research project that started in December 2009. Its objective is to develop an innovative, highly efficient and productive design methodology implemented in a holistic framework for iteratively exploring the design space of embedded hardware/software (HW/SW) systems. Rising heterogeneity and complexity of embedded systems result in gaps and defines challenges to be faced. These challenges include:

  • handling complexity of execution platforms and applications
  • uncertainty of platform selection and application to platform mapping
  • balancing between increasing power consumption, possible performance, and explicit application needs
  • meeting memory demands both in size and access times

High performance usually causes high power consumption. A main challenge in today's embedded system design is to find a suitable balance between performance and power consumption. Until now, no generic framework is available that can perform an accurate and jointly estimation of performance and power consumption starting at the algorithmic level. In custom hardware design, advances in performance and power consumption have been mainly influenced by new technologies and an evolution in design methodology. The latter was achieved by several important steps in increasing the level of abstraction for the design entry. All these steps gave the productivity in hardware design a boost. They made it possible to manage the steadily growing complexity of integrated circuits.

Software processing units like micro controllers, SIMD processors or DSPs have been made more efficient. Modern platforms support advanced power management capabilities with dynamic frequency scaling and power islands that needs to be effectively controlled to maximise the optimization potential.

All the challenges induced by modern systems and mentioned above are addressed in COMPLEX. COMPLEX will provide a holistic framework and design flow. The framework can be divided in five main stages:

  • MDA design entry: MARTE UML Profile, Stateflow and Simulink support
  • Executable specification: Executable system specification in SystemC; input stimuli derived by MARTE use-case specification; IP-XACT platform specification for IP component view
  • Estimation & model generation: HS/SW task separation & test bench generation; automatic source analysis including behavioural synthesis and cross compilation; RTL IP component model integration; virtual platform generator with TLM2 interface synthesis
  • Overall system simulation: Enables high-speed simulation including OSCI TLM2 with meta data (power, delay) annotations, down to bus-cycle accurate simulation, includes self-simulating timing and power models
  • Exploration & Optimisation: Simulation trace analysis; connection to automatic exploration, visualization and reporting; hints for optimisations during application and platform refinement
COMPLEX design process
COMPLEX design process

Using a very abstract design entry, combined with an automatic generation of virtual systems allows a fast design space exploration. The availability of this new design entry in conjunction with the traditional bottom-up approach defines a new viewpoint for the design of embedded systems: How to find a mapping and implementation of an application onto an execution platform that fulfils all functional and non-functional requirements at minimal cost. To avoid expensive redesigns and costly code modifications, the platform decision should be done before investing money into a concrete target platform. For this purpose reliable information about the execution behaviour of the application running on the platform in terms of functionality, performance and power consumption are absolutely mandatory. In COMPLEX available point-tools and pre-designed system components are bundled and properly integrated into a holistic framework for platform-based design space exploration:

  • Behavioural synthesis for the generation of custom hardware from algorithmic descriptions.
  • Dedicated embedded SW compilers for the generation of executables from algorithmic descriptions.
  • Portfolio of HW intellectual property, ranging from microprocessors, DSPs, memories, on-chip communication structures, communication peripherals, and domain specific accelerators.
  • Virtual platforms for early system simulation, analysis and integration of HW and SW components without using costly test-chips.

The motivation of COMPLEX is to build a framework on top of these assets that supports a software-like design entry. It integrates platforms and software development tool-chains from different European providers, and incorporates European EDA tools and know-how in the area of power and timing estimation of HW, SW and run-time power management. The project outcome is the connection of this framework to the next-generation system specification and design methodology, the automatic generation of an efficient executable virtual system, giving accurate and reliable timing and power information, and the integration of an automatic design space exploration for finding the optimal design space instance parameters.

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