Kai-Hylla.de  

Last Update: 03 Jun 2018

As part of my scientific work I have been (co-)author of several conference papers and articles. You will find the contributions together with an abstract and a citation here. At the end of this page you will also find a list of conferences and journals, for which I did some reviews.

Download all entries as BIBTEX

  • 2014

    • July 2014

      An ESL Timing & Power Estimation and Simulation Framework for Heterogeneous SoCs (in english)

      Abstract

      Consideration of an embedded system’s timing behaviour and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. But prediction of the composed system behaviour can hardly be made without considering all system components. In this paper we present an ESL framework for timing and power aware rapid virtual system prototyping of heterogeneous SoCs consisting of software, custom hardware and 3rd party IP components. Our proposed flow combines system-level timing and power estimation techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from a functional C/C++ description, which then allows to study different platforms, mapping alternatives, and power management strategies. We propose an efficient code annotation technique for timing and power, that enables fast host execution and collection of power traces, based on domain-specific workload scenarios.
      This paper was presented at the International Conference on Embedded Computer Systems: Architectures, Modelling ans Simulation (SAMOS), which took place from July 14 to 17 at Samos Island, Greece.

      Citation

      Grüttner, Kim; Hartmann, Philipp A.; Fandrey, Tiemo; Hylla, Kai; Lorenz, Daniel; Stattelmann, Stefan; Sander, Björn; Bringmann, Oliver; Nebel, Wolfgang; and Rosenstiel, Wolfgang: An ESL Timing & Power Estimation and Simulation Framework for Heterogeneous SoCs. July 2014,
    • May 2014

      Considering Variation and Aging in a Full Chip Design Methodology at System Level (in english)

      Abstract

      We present a new system-level design methodology enabling the consideration of process variations and degradation due to aging in early stages of the design process. By mapping an executable system specification to SoC processing, communication and memory components in combination with component wise timing and power characterization with a source-level back-annotation, we enable efficient full SoC power and temperature over time simulations. Based on the resulting temporal and spatial power and temperature distribution we use a high-level multi-physics simulation to assess the impact of degradation and aging. We evaluate our approach using an ARM7 based SoC design.
      This paper was presented at the 2014 Electronic System Level Synthesis Conference (ESLsyn), which took place from May 31 to June 1 at San Francisco, USA and was co-located with DAC.

      Citation

      Helms, Domenik; Grüttner, Kim; Eilers, Reef; Metzdorf, Malte; Hylla, Kai; Poppen, Frank; and Nebel, Nebel: Considering Variation and Aging in a Full Chip Design Methodology at System Level. May 2014.
    • January 2014

      Bridging the Gap between Precise RT-Level Power/Timing Estimation and Fast High-Level Simulation: A method for automatically identifying and characterising combinational macros in synchronous sequential systems at register-transfer level and subsequent executable high-level model generation with respect to non-functional properties (in english)

      Keywords

      electronic design automation, power estimation, model generation, combinational macro, sequential circuit, combinational circuit, high-level synthesis

      Citation

      Hylla, Kai: Bridging the Gap between Precise RT-Level Power/Timing Estimation and Fast High-Level Simulation: A method for automatically identifying and characterising combinational macros in synchronous sequential systems at register-transfer level and subsequent executable high-level model generation with respect to non-functional properties. Pages: 255, January 2014, doctoral thesis. URN:urn:nbn:de:gbv:715-oops-19242
  • 2013

    • November 2013

      The COMPLEX reference framework for HW/SW Co-Design and Power Management Supporting Platform-Based Design-Space Exploration (in english)

      Abstract

      The consideration of an embedded device’s power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of today’s heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators.

      As a result, we propose a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives, and power management strategies.

      Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off analysis between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed framework and design flow has been implemented in the COMPLEX FP7 European integrated project.

      Citation

      Grüttner, Kim; Hartmann, Philipp A.; Hylla, Kai; Rosinger, Sven; Nebel, Wolfgang; Herrera, Fernando; Villar, Eugenio, Brandolese, Carlo; Fornaciari, William; Palermo, Gianluca; Ykman-Couvreur, Chantal; Quaglia, Davide; Ferrero, Francisco; and Valencia, Raúl: The COMPLEX reference framework for HW/SW Co-Design and Power Management Supporting Platform-Based Design-Space Exploration. Microprocessors and Microsystems, Elsevier Pages: 966 - 980, November 2013. DOI:10.1016/j.micpro.2013.09.001

      This article is a available at ScienceDirect.
    • March 2013

      Early Power & Timing Estimation of Custom Hardware Blocks based on Automatically Generated Combinatorial Macros (in english)

      Abstract

      In this paper we present a technique for automatically estimating power and timing of full-custom hardware blocks, such as co-processors or hardware accelerators from algorithmic descriptions. The required characterisation is performed on a cycle-accurate functional description at register transfer level, which is obtained from a high-level synthesis. Characterisation results are used for generating a power and timing aware high-level simulation model. As an abstraction step, combinatorial macros are identified and characterised automatically. Characterisation takes place using RT-level power models, providing accurate estimates. Using the characterised macros, a power and timing annotated high-level simulation model is generated. This C++-based virtual prototype allows a fast, yet accurate estimation of the given design. Having a total error of about 3.6% we achieve a speed-up of approximately 516x compared to an RT-level estimation, while giving cycle-accurate timing and power estimates.

      Citation

      Hylla, Kai; Hartmann, Philipp A.; Helms, Domenik; and Nebel, Wolfgang: Early Power & Timing Estimation of Custom Hardware Blocks based on Automatically Generated Combinatorial Macros. March 2013.
  • 2012

    • September 2012

      COMPLEX – COdesign and power Management in PLatform-based design space EXploration (in english)

      Abstract

      The consideration of an embedded device’s power consumption and its management is increasingly important nowadays. Currently, it is not easily possible to integrate power information already during the platform exploration phase. In this paper, we discuss the design challenges of today’s heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators. As a result, we propose a design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping. Virtual executable prototypes are generated from MARTE/UML and functional C/C++ descriptions, which then allows to study different platforms, mapping alternatives and power management strategies. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. We propose an efficient code annotation technique for timing and power properties that enables fast host execution as well as adaptive collection of power traces. Combined with a flexible design-space exploration (DSE) approach our flow allows a trade-off between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed flow is currently under implementation in the COMPLEX FP7 European integrated project.

      Notes

      This invited paper was presented on the Euromicro Conference on Digital System Design (DSD’12), which took place from 5 to 8 September 2012 in Cesme, Izmir, Turkey.
      Download the programme

      Citation

      Grüttner, Kim; Hartmann, Philipp A.; Hylla, Kai; Rosinger, Sven; Brandolese, Carlo; Fornaciari, William; Palermo, Gianluca; Quaglia, Davide; Nebel, Wolfgang; Ykman-Couvreur, Chantal; Ferrero, Francisco; Valencia, Raúl; Herrera, Fernando; and Villar, Eugenio: COMPLEX – COdesign and power Management in PLatform-based design space EXploration. Euromicro Conference on Digital System Design (DSD’12) September 2012.
    • September 2012

      NEEDS – Nano-Electronics design for 3D systems (in deutsch)

      Abstract

      High-density nanoelectronics consisting of heterogeneous components provide economies of resources and thus cost savings in many application scenarios. They also provide a large number of opportunities and options during the design process. The German Federal Ministry of Education and Research (BMBF) funded project NEEDS provides such a comprehensive process. Tools from different domains such as design methodology, circuit generation, but also from the area of application-specific technology planning, as well as design analysis and test of 3D-Chips are developed and combined. The result is a design process, using specialized and sophisticated tools to achieve a good overall solution. The different optimization goals of the individual tools are weighted against each other in an iterative design space exploration. The optimization of a 3D-Chip is possible in a holistic and interdisciplinary way.

      Note

      This paper will be presented at the Zuverlässigkeit und Entwurf 2012, which will take place from 23. to 26. September in Bremen.
      Download the programme

      Citation

      Hylla, Kai; Metzdorf, Malte; Grünewald, Armin; Hahn, Kai; Heinig, Andy; Knöchel, Uwe; Wolf, Susann; Miller, Felix; Wild, Thomas; Quiring, Artur; Olbrich, Markus; Sattler, Sebastian; and Treytnar, Dieter: NEEDS – Nanoelektronik-Entwurf für 3D-Systeme. Zuverlässigkeit und Entwurf (ZuE’12), September 2012.

      This paper is available at VDE-Verlag. Conference participants can download the presented slides.
    • 2012

      Rapid Prototyping of Complex HW/SW Systems using a Timing and Power Aware ESL Framework (in english)

      Abstract

      Consideration of an embedded system’s timing behaviour and power consumption at system-level is increasingly important nowadays but it is also an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. But prediction of the composed system behaviour can hardly be made. In this paper we present the concept of an ESL framework for timing and power aware rapid virtual system prototyping of embedded HW/SW systems. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. Our proposal aims at the generation of executable virtual prototypes from a functional C/C++ specification. These prototypes are enriched by static and dynamic power values as well as execution times. This efficient code annotation technique enables a fast host and allows a trade-off between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed flow will be implemented in the COMPLEX FP7 European integrated project.

      Notes

      This chapter will appear in System Specification and Design Languages: Selected Contributions from FDL’2010 and is an extended version of Towards an ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems, listed below.

      Citation

      Grüttner, Kim; Hylla, Kai; Rosinger, Sven; and Nebel, Wolfgang: Rapid Prototyping of Complex HW/SW Systems using a Timing and Power Aware ESL Framework. System Specification and Design Languages: Selected Contributions from FDL’2010 2012. DOI:10.1007/978-1-4614-1427-8_10
  • 2011

    • March 2011

      Enabling Timing and Power Aware Virtual Prototyping of HW/SW Systems (in English)

      Abstract

      We propose the concept of an ESL framework for timing and power aware rapid virtual system prototyping of embedded HW/SW systems. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. Our proposal aims at the generation of executable virtual prototypes from a functional C/C++ specification. These prototypes are enriched by static and dynamic power values as well as execution times. They allow a trade-off between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios.

      Notes

      This poster was presented on the Design, Automation & Test in Europe 2011 (DATE’11), which took place from 14 to 18 March in Grenoble, France.
      Download the programme

      Citation

      Grüttner, Kim; Hylla, Kai; Rosinger, Sven; and Hartmann, Philipp A.: Enabling Timing and Power Aware Virtual Prototyping of HW/SW Systems. Design, Automation & Test in Europe 2011 (DATE’11) March 2011. Extended abstract and poster
  • 2010

    • September 2010

      Towards an ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems (in English)

      Keywords

      system level power and timing estimation, design space exploration

      Abstract

      Consideration of an embedded system’s timing behaviour and power consumption at system-level is an ambitious task. Sophisticated tools and techniques exist for power and timing estimations of individual components such as custom hard- and software as well as IP components. But prediction of the composed system behaviour can hardly be made. In this paper we present the concept of an ESL framework for timing and power aware rapid virtual system prototyping of embedded HW/SW systems. Our proposed flow combines system-level timing and power estimation techniques available in commercial tools with platform-based rapid prototyping. Our proposal aims at the generation of executable virtual prototypes from a functional C/C++ specification. These prototypes are enriched by static and dynamic power values as well as execution times. They allow a trade-off between different platforms, mapping alternatives, and optimization techniques, based on domain-specific workload scenarios. The proposed flow will be implemented in the COMPLEX FP7 European integrated project.

      Notes

      This paper was presented on the Forum on specification and Design Languages (FDL), which took place from 14 to 16 September 2010 in Southampton, UK.
      Download the programme

      Citation

      Grüttner, Kim; Hylla, Kai; Rosinger, Sven; and Nebel, Wolfgang: Towards an ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems. Forum on Specification, Verification and Design Languages (FDL’10), September 2010. DOI:10.1049/ic.2010.0129
  • 2009

    • September 2009

      Logical-Statistical Simulation with Thermal and Voltage Mapping for Variation and Degradation Prediction (in German)

      Keywords

      System-level estimation, thermal modeling, IR-drop, reliablility, electro-thermal coupling

      Abstract

      We present a statistical description of digital systems that predicts the system’s behavior over the entire life cycle as a result of a previously performed clock-cycle-accurate simulation. The simulator considers interactions between power dissipation (static and dynamic), temperature- and voltage distribution as well as various degradation effects. Since the influence of global manufacturing variations on these interactions and the system speed can be taken into account, a forecast of the average behavior of many systems in terms of functional and parametric faults on the production and during the lifetime of the system is possible.

      Notes

      This paper was presented at Zuverlässigkeit und Entwurf 2009, which took place at Stuttgart from 21 September till 23 September 2009.
      Download the programme

      Citation

      Helms, Domenik; Hylla, Kai; and Nebel, Wolfgang: Logical-Statistical Simulation with Thermal and Voltage Mapping for Variation and Degradation Prediction. Zuverlässigkeit und Entwurf 2009 (ZuE’09), September 2009. In German.

      Proceedings are available from VDE-Verlag.
    • August 2009

      Hybrid Logical-Statistical Simulation with Thermal and IR-Drop Mapping for Degradation and Variation Prediction (in English)

      Keywords

      System level estimation, thermal modelling, IR-drop, reliability, electro-thermal coupling

      Abstract

      We present a statistical life-time description for digital systems, which is characterized by short term functional simulation. Temperature and IR-drops for each hardware task of the system are regarded based on a coarse RT-floor plan and a component wise prediction of the dynamic and leakage power. By iteratively updating threshold voltage and supply resistances, then dynamic and leakage power, then temperature and IR-drop distribution, electro-thermal coupling as well as long term degradation effects can be described.

      Note

      This paper was presented on the International Symposium on Low Power Electronics and Design 2009, which took place in San Francisco, California, USA from 19 August to 21 August 2009.
      Download the programme

      Citation

      Helms, Domenik; Hylla, Kai; and Nebel, Wolfgang: Hybrid Logical-Statistical Simulation with Thermal and IR-Drop Mapping for Degradation and Variation Prediction. International Symposium on Low Power Electronics and Design 2009 (ISLPED’09), August 2009.

      The article be downloaded at ACM.
    • May 2009

      An Advanced Simulink Verification Flow Using SystemC (in English)

      Keywords

      SystemC, Simulink, verification, co-simulation, test bench

      Abstract

      Functional verification is a major part of today’s system design task. Several approaches are available for verification on a high abstraction level, where designs are often modelled using MATLAB/Simulink, as well as for RT-level verification. Different approaches are a barrier to a unified verification flow. For simulation based RT-level verification, an extended test bench concept has been developed at Robert Bosch GmbH. This paper describes how this SystemC-based concept can be applied to Simulink models. The implementation of the resulting verification flow addresses the required synchronization of both simulation environments, as well as data type conversion. An example is used to evaluate the implementation and the whole verification flow. It is shown that using the extended verification flow saves a significant amount of time during development. Reusing test bench modules and test cases preserves consistency of the test bench. Verification is done automatically rather than by inspecting the waveform manually. The extended verification flow unifies system-level and RT-level verification, yielding a holistic verification flow.

      Note

      This chapter appears in Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL’08 and is an extended version of Using SystemC for an extended MATLAB/Simulink verification flow, listed below.

      Citation

      Hylla, Kai; Oetjens, Jan-Hendrik; and Nebel, Wolfgang: An Advanced Simulink Verification Flow Using SystemC. In Martin Radezki, editor Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL’08. Springer, May 2009.

      This book is available at Springer. An excerpt from the book can be found on Google books.
  • 2008

    • September 2008

      Using SystemC for an extended MATLAB/Simulink verification flow (in English)

      Keywords

      SystemC, Simulink, verification, synchronization, data conversion

      Abstract

      Functional verification is a major part of today’s system design task. Several approaches are available for verification on a high abstraction level, where designs are often modelled using MATLAB/Simulink, as well as for RT-level verification. Different approaches are a barrier to a unified verification flow. For simulation based RT-level verification, an extended test bench concept has been developed at Robert Bosch GmbH. This paper describes how this SystemC-based concept can be applied to Simulink models. The implementation of the resulting verification flow addresses the required synchronization of both simulation environments, as well as data type conversion. An example is used to evaluate the implementation and the whole verification flow. It is shown that using the extended verification flow saves a significant amount of time during development. Reusing test bench modules and test cases preserves consistency of the test bench. Verification is done automatically rather than by inspecting the waveform manually. The extended verification flow unifies system-level and RT-level verification, yielding a holistic verification flow.

      Note

      This paper was presented on the Forum on Specification, Verification and Design Languages, 2008. FDL 2008. 23 September to 25 September 2008 in Stuttgart, Germany.
      Download the programme

      Citation

      Hylla, Kai; Oetjens, Jan-Hendrik; and Nebel, Wolfgang: Using SystemC for an extended MATLAB/Simulink verification flow. Forum on Specification, Verification and Design Languages 2008 (FDL’08). 23-25 Sept, 2008, Pages: 221 - 226. DOI: 10.1109/FDL.2008.4641449

      This paper is available at IEEE Xplore.
    • April 2008

      Extending a VHDL/SystemC verification environment for application on MATLAB/Simulink models (in German)

      Keywords

      SystemC, Simulink, verification, synchronization, data conversion

      Abstract

      Functional verification is one of the most important steps in today’s industrial system design task. Errors, discovered late slow down development, increase time-to-market and cause unbudgeted costs. System failures after rollout damage the company’s image and may harm material and in the worst case even live. A lot of effort is made to avert these risks. Functional verification presents up to 70% of the total effort and thus a major part of today’s system design task. Several approaches are available for verification on a high abstraction level, where designs are often modelled using MATLAB/Simulink, as well as for RT-level verification. Different approaches inhibit a unified verification flow.

      For simulation-based RT-level verification, an extended test bench concept has been developed at Robert Bosch GmbH. This diploma thesis describes how this SystemC-based concept can be applied to Simulink models. Extended test bench modules can be used as part of the Simulink model, allowing an automatic verification of the design. The benefits and advantages of the extended verification flow are shown. The implementation of the flow addresses the required synchronization of both simulation environments, as well as data type conversion. Synchronization is done depending on the structure of the test bench modules, in order to reach a good performance of the simulation. Different types of data type conversion help to bridge the gap between the levels of abstraction. Examples are used to evaluate the implementation and the whole verification flow. It is shown that using the extended verification flow saves a significant amount of time during development. Reusing test bench modules and test cases preserves consistency of the verification environment. Verification is done automatically rather than by inspecting the waveform manually. The extended verification flow unifies system-level and RT-level verification, yielding a holistic verification flow.

      Citation

      Hylla, Kai: Erweiterung einer VHDL/SystemC-Verifikationsumgebung zur Anwendung auf MATLAB/Simulink-Modelle. Masters Thesis, April 2008, Pages: 109. In German.
  • 2006

    • August 2006

      Evaluation of bus-based communication protocols in SoC-design and conceptual design of an abstract interface (in German)

      Keywords

      Communication, system-on-a-chip, AMBA, CoreConnect, OPB, Wishbone

      Citation

      Hylla, Kai: Evaluierung busbasierter Kommunikationsprotokolle im SoC-Design und Entwurf eines abstrakten Interfaces. August 2006, Pages: 69. In German.